It is well known that some integrated circuit technologies are susceptible to damage by electrostatic discharge (ESD). CMOS transistors which are frequently used in logic circuits are an example of such devices. Protection schemes are known, such as providing diodes connecting an input pin to the device supply rails. However these measures are crude and can switch into a conducting state during normal operating conditions.
More sophisticated ESD protection circuits have been implemented using transistors within an integrated circuit. However, the transistor parameters and fabrication processes used in these integrated ESD protection circuits have not typically been optimized for their ESD function. Instead, the performance characteristics of these ESD transistors have largely been dependent upon fabrication parameters chosen to optimize other transistors that carry out the primary function of the circuit to be protected. Therefore, it has mainly been a matter of luck whether the fabrication parameters chosen to optimize majority devices are suitable for use in the accompanying ESD protection circuit. While it is possible to separately optimize an ESD protection circuit using additional processing steps, those additional processing steps carry increased costs. Instead, a reliable method of tailoring ESD protection device performance without using additional processing steps is required.